Verilog / SystemVerilog IC Design / Verification Engineer

Alphadesign AI 未验证

多个城市, 巴基斯坦

发布 Jul 11, 2024 270 查看

PKR. 200,000 - 200,000/Month

We are seeking a highly skilled and motivated Verilog/SystemVerilog IC Design and Verification Engineer to join our dynamic team at Alphadesign Pakistan. The ideal candidate will have a strong background in digital design and verification, with a passion for developing cutting-edge integrated circuits.

Key Responsibilities:

Design and Implementation:

  • Develop and implement digital IC designs using Verilog and SystemVerilog.
  • Create and optimize RTL code for high-performance, low-power applications.
  • Perform logic synthesis, place and route, and timing analysis.

Verification:

  • Develop and execute comprehensive verification plans to ensure the functionality and performance of IC designs.
  • Create and maintain testbenches, test cases, and simulation models using SystemVerilog/UVM.
  • Identify and debug design issues using industry-standard verification tools and methodologies.

Collaboration:

  • Work closely with cross-functional teams, including system architects, software engineers, and hardware engineers, to define and refine design specifications.
  • Participate in design reviews, providing constructive feedback and suggestions for improvement.

Documentation and Reporting:

  • Prepare detailed design documentation, including specifications, test plans, and reports.
  • Present verification results and progress updates to stakeholders.

Qualifications:

Education:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Experience:

  • 1+ years of experience in digital IC design and verification prefered, fresh graduate also welcomed
  • Proficiency in Verilog and SystemVerilog, with a strong understanding of digital design principles.

Skills:

  • Experience with ASIC/FPGA design flow and EDA tools (e.g., Synopsys, Cadence).
  • Strong problem-solving and analytical skills.
  • Excellent communication and teamwork abilities.
  • Familiarity with scripting languages (Python, Perl, Tcl) is a plus.

Preferred:

  • Knowledge of UVM and experience with formal verification techniques.

Benefits:

  • Competitive salary and comprehensive benefits package.
  • Opportunities for professional growth and development.
  • Collaborative and innovative work environment

工作详细内容

全部职位:
10 发布
工作时间:
早班
工作类型:
性别:
没有偏好
最低学历:
学士
职位等级:
入门级
电话预约已成功,我们的专家会在短时间内与你联系:
� 经验
在之前申请:
Aug 12, 2024
发布日期:
Jul 11, 2024

Alphadesign AI

· 1-10 员工 - 伊斯兰堡, 卡拉奇, 拉合尔, 亚兹曼曼迪

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